IEEE Transactions on Computers
A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
System Design with SystemC
Reconfigurable Instruction Set Processors from a Hardware/Software Perspective
IEEE Transactions on Software Engineering
System Level Design of Reconfigurable Systems-on-Chip
System Level Design of Reconfigurable Systems-on-Chip
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Supporting multiple-input, multiple-output custom functions in configurable processors
Journal of Systems Architecture: the EUROMICRO Journal
RoSA: a reconfigurable stream-based architecture
Proceedings of the 20th annual conference on Integrated circuits and systems design
A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications
AHS '07 Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems
Using traditional loop unrolling to fit application on a new hybrid reconfigurable architecture
Proceedings of the 2008 ACM symposium on Applied computing
The reconfigurable instruction cell array
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Study on the Multi-pipeline Reconfigurable Computing System
CSSE '08 Proceedings of the 2008 International Conference on Computer Science and Software Engineering - Volume 04
Processor Design: System-On-Chip Computing for ASICs and FPGAs
Processor Design: System-On-Chip Computing for ASICs and FPGAs
Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays
SASP '08 Proceedings of the 2008 Symposium on Application Specific Processors
Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications
Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications
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In this work, we explore a new family of coarse grain reconfigurable architecture called BRICK, which is capable of mapping complete expressions and pipelines into one processing element with Multiple-Input, Multiple-Output characteristics while provided with a centralized control unit to synchronize the operation of each Processing Element (PE). Each PE has heterogeneous ALUs specialized in a particular type of operation. These ALUs can be interconnected to implement complex expressions, either sequential or combinational, increasing computational density and utilization rate of the reconfigurable Array. Preliminary synthesis results and application examples show that efficient mappings can be achieved with BRICK.