Exploring many-core design templates for FPGAs and ASICs

Authors:
Ilia Lebedev;Christopher Fletcher;Shaoyi Cheng;James Martin;Austin Doupnik;Daniel Burke;Mingjie Lin;John Wawrzynek
Affiliations:
CSAIL, Massachusetts Institute of Technology, Cambridge, MA;CSAIL, Massachusetts Institute of Technology, Cambridge, MA;Department of EECS, University of California at Berkeley, CA;Department of EECS, University of California at Berkeley, CA;Department of EECS, University of California at Berkeley, CA;Department of EECS, University of California at Berkeley, CA;Department of EECS, University of California at Berkeley, CA;Department of EECS, University of California at Berkeley, CA
Venue:
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
Year:
2012

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Abstract

We present a highly productive approach to hardware design based on a many-coremicroarchitectural template used to implement compute-bound applications expressed in a high-level data-parallel language such as OpenCL. The template is customized on a per-application basis via a range of high-level parameters such as the interconnect topology or processing element architecture. The key benefits of this approach are that it (i) allows programmers to express parallelism through an API defined in a high-level programming language, (ii) supports coarse-grained multithreading and fine-grained threading while permitting bit-level resource control, and (iii) reduces the effort required to repurpose the systemfor different algorithms or different applications. We compare template-driven design to both full-custom and programmable approaches by studying implementations of a compute-bound data-parallel Bayesian graph inference algorithm across several candidate platforms. Specifically, we examine a range of template-based implementations on both FPGA and ASIC platforms and compare each against full custom designs. Throughout this study, we use a general-purpose graphics processing unit (GPGPU) implementation as a performance and area baseline. We show that our approach, similar in productivity to programmable approaches such as GPGPU applications, yields implementations with performance approaching that of full-custom designs on both FPGA and ASIC platforms.