The connection machine
Global optimization and simulated annealing
Mathematical Programming: Series A and B
Regular partitioning for synthesizing fixed-size systolic arrays
Integration, the VLSI Journal
Linear mappings of n-dimensional uniform recurrences onto k-dimensional systolic arrays
Journal of VLSI Signal Processing Systems
IEEE Transactions on Software Engineering - Special issue on architecture-independent languages and software tools for parallel processing
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
NAPA C: Compiling for a Hybrid RISC/FPGA Architecture
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
The NAPA Adaptive Processing Architecture
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Heterogeneity as Key Feature of High Performance Computing: the PQE1 Prototype
HCW '00 Proceedings of the 9th Heterogeneous Computing Workshop
Evolutionary search for low autocorrelated binary sequences
IEEE Transactions on Evolutionary Computation
High Level Synthesis for Programmable Devices: The HADES Project
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
OREN: Optimal revocations in ephemeral networks
Computer Networks: The International Journal of Computer and Telecommunications Networking
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We describe a design methodology which allows a fast design and prototyping of dedicated hardware devices to be used in heterogeneous computations. The platforms used in heterogeneous computations consist of a general-purpose COTS architecture which hosts a dedicated hardware device; parts of the computation are mapped onto the former, parts onto the latter, in a way to improve the overall computation efficiency. We report the design and the prototyping of a FPGA-based hardware board to be used in the search of low-autocorrelation binary sequences. The circuit has been designed by using a recently developed Parallel Hardware Generator (PHG) package which produces a synthesizable VHDL code starting from the specific algorithm expressed as a System of Affine Recurrence Equations (SARE). The performance of the realized devices has been compared to those obtained on the same numerical application on several computational platforms.