On mapping parallel algorithms into parallel architectures
Journal of Parallel and Distributed Computing
Computing
Communications of the ACM
The Garp Architecture and C Compiler
Computer
CODACS Project: A Demand-Data Driven Reconfigurable Architecture (Research Note)
Euro-Par '02 Proceedings of the 8th International Euro-Par Conference on Parallel Processing
High Level Compiling for Low Level Machines
PACT '93 Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism
A Functional Data-flow Architecture Dedicated to Real-time Image Processing
PACT '93 Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism
NAPA C: Compiling for a Hybrid RISC/FPGA Architecture
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
D3AS project: a different approach to the manycore challenges
Proceedings of the 9th conference on Computing Frontiers
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In this paper, we present CHIARA, the programminglanguage used to program CODACS (a general purposedataflow architecture exploiting FPGA technology), and describethe compiling strategies leading from CHIARA programsto the CODACS dataflow graphs. CHIARA is a functionalprogramming language based on Backus'FP. We designedboth the language and the compiling tools in such away that CHIARA programs can be efficiently compiled andrun onto the overall architecture and CODACS platform-processorsbeing, for the latter, also the low-level (assembly)programming language.Some preliminary experimental results are discussed,demonstrating that the CHIARA approach to CODACS programmingis feasible and promising.