Communicating sequential processes
Communicating sequential processes
Computer imaging recipes in C
Memory Access Optimization and RAM Inference for Pipeline Vectorization
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
NAPA C: Compiling for a Hybrid RISC/FPGA Architecture
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
The NAPA Adaptive Processing Architecture
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Towards provably correct hardware/software partitioning using occam
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
This paper presents task-parallel programming, a style of application development for reconfigurable systems. Task-parallel programming enables efficient interaction between concurrent hardware and software tasks. In particular, it supports description of communication and computation tasks running in parallel to allow effective implementation of designs where data transfer time between hardware and software components is comparable to computation time. This approach permits precise specification of parallelism without requiring hardware design knowledge. We present language extensions for task-parallel programming, inspired by the occam and Handel languages. A compilation scheme for this method is described: the four main stages are memory mapping, channel implementation, software generation and hardware synthesis. Our techniques have been evaluated using video applications on the RC1000-PP hardware platform.