RAT: RC Amenability Test for Rapid Performance Prediction
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Platform-aware bottleneck detection for reconfigurable computing applications
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Many signal processing algorithms are known to suffer from super-linear increases in computational time with increasing data size and number of signals being processed. This behavior is particularly true for the Parzen window-based, non-parametric estimation algorithm for Probability Density Function (PDF). It forms an integral part of numerous machine-learning applications and hence fast and efficient execution of the algorithm is highly desirable. FPGAs have been successfully used for computationally intensive problems in a wide variety of scientific domains to achieve speedup over traditional software implementations. This paper describes the design, development and analysis of a multi-dimensional PDF estimation algorithm using Gaussian kernels on FPGAs. First, preliminary analyses are performed to predict the algorithm’s amenability to a hardware paradigm and likely speedups are determined. Actual speedup and performance metrics obtained are tabulated and compared to the predictions. We obtained a speedup on the order of 20x over a 3.2GHz processor. Multi-core architectures are developed to improve performance by scaling the design. Portability of the hardware design across multiple FPGA platforms is also analyzed. This work is further valuable in that due to structural similarities between many signal and image processing algorithms and the PDF algorithm, the architecture could potentially be reused for their rapid development on FPGAs