Instrumenting Bitstreams for Debugging FPGA Circuits

Authors:
Paul Graham;Brent Nelson;Brad Hutchings
Affiliations:
Brigham Young University;Brigham Young University;Brigham Young University
Venue:
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Year:
2001

Citing 0
Cited 11

High-Visibility Debug-By-Design for FPGA Platforms

The Journal of Supercomputing
Scan-chain based watch-points for efficient run-time debugging and verification of FPGA designs

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Performance analysis challenges and framework for high-performance reconfigurable computing

Parallel Computing
Design, Debug, Deploy: The Creation of Configurable Computing Applications

Journal of Signal Processing Systems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
From Silicon to Science: The Long Road to Production Reconfigurable Supercomputing

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Performance Analysis Framework for High-Level Language Applications in Reconfigurable Computing

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Smalltalk debug lives in the matrix

IWST '10 International Workshop on Smalltalk Technologies
Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers

Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Leveraging reconfigurability to raise productivity in FPGA functional debug

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Accelerating FPGA debug: Increasing visibility using a runtime reconfigurable observation and triggering network

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Quantified Score

Hi-index	0.01

Visualization

Abstract

Since FPGAs are frequently used to improve the time to market for products, shortening the time for validating and debugging FPGA designs is, thus, important. Our paper discusses how directly instrumenting FPGA programming data, or bitstreams, with debugging hardware can improve the debugging productivity for designers and, thus, reduce a designýs time to market. We also provide some background relating to the current state of the art in debugging FPGA designs and describe how bitstream instrumentation can be automated using JHDL, JBits and JRoute. When instrumenting designs with embedded logic analyzers at the bitstream level, we have witnessed design modification speed-ups ranging from about 6 to 19 times over more conventional techniques. We will also briefly mention other applications of bitstream modification in debugging FPGA designs.