Scan-chain based watch-points for efficient run-time debugging and verification of FPGA designs

Authors:
Anurag Tiwari;Karen A. Tomko
Affiliations:
University of Cincinnati, Cincinnati, OH;University of Cincinnati, Cincinnati, OH
Venue:
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Year:
2003

Citing 5
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Abstract

This paper describes a structured and area efficient approach for in-situ debugging of application for FPGA based reconfigurable systems. A scan chain is inserted into the hardware design running on the FPGA, which helps in debugging and verification by providing watch-point capability. The scan chain technique proposed is easy to use and has very low overhead. The scan-chain based implementation capitalizes on the capability of newer FPGAs to connect several LUTs serially and configure them as shift registers. The hardware debugging procedure proposed using the shift register LUTs does not require any recompilation of the design to change the watch-point conditions and thus, is very fast. In this paper the area overhead resulting from addition of a scan-chain based watch-point logic is discussed and is compared with other proposed debugging techniques. We observed that this technique has an average area overhead of 46% for the ITC benchmark circuits with varying widths of watch-point signals.