Unifying simulation and execution in a design environment for FPGA systems

Authors:
Brad L. Hutchings;Brent E. Nelson
Affiliations:
Brigham Young Univ., Provo, UT;Brigham Young Univ., Provo, UT
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Year:
2001

Citing 0
Cited 3

Scan-chain based watch-points for efficient run-time debugging and verification of FPGA designs

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
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Long-term on-chip verification of systems with logical events scattered in time

Microprocessors & Microsystems

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Abstract

Field programmable gate array (FPGA)-based systems provide advantages over conventional hardware including: (1) availability of the hardware during design and debug; (2) programmability; and (3) visibility. These three advantages can greatly shorten the design and verification cycle. This paper discusses a design environment that exploits these three FPGA-specific advantages to create a unified simulation/execution debug environment implemented in the JHDL design system. The described system provides a hardware debugging environment with the functionality of a simulator but up to 10000/spl times/ faster. In addition, testbenches and other typical verification software used in simulators can be used to verify running hardware.