ISSS '00 Proceedings of the 13th international symposium on System synthesis
UML-based multiprocessor SoC design framework
ACM Transactions on Embedded Computing Systems (TECS)
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Hardware synthesis of SDL models poses several problems, because SDL uses Communicating Sequential Processes (CSP) paradigm for system specification. It allows dynamic processes and its semantics assume an infinite FIFO buffer at the input of each process for inter-process communication. We had presented a methodology in [6,7,8] and later refined it in [9], for efficient hardware synthesis from SDL specification. In this paper, we describe the experience of applying this methodology to a large case study. The case study is an ATM Multiplexer which exhibits a complex control flow and uses large tables. It was modelled using multiple processes. Hardware synthesis was carried out using the methodology starting from its SDL model. The results show that the methodology leads to a correct and efficient hardware implementation. In particular, the methodology avoids use of costly FIFO buffers for implementing inter-process communication and allows sharing of hard ware resources among various instances of the same process. The final implementation also meets the 155 Mbit/sec data rate performance requirement