FunState—an internal design representation for codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 4th ACM international conference on Embedded software
Hierarchical finite state machines with multiple concurrency models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Due to the heterogeneity of network processor architectures and constantly evolving network applications, it is currently a challenge to characterize the network processor workloads. In this paper, we formally model the task-level workloads of network processors as reactive dataflow process network (RDPN). RDPN is a suitable model of computation for formally describing the behaviors of packet-level parallel processing and event interaction with control point of network processors. We extend the expressive capability of RDPN by using three transformations (i.e., clustering, decomposing and duplicating) to analyze the model and support the further design space exploration of network processors.