Coherence and satisfiability of waveform timing specifications
Coherence and satisfiability of waveform timing specifications
Logic Circuits and Microcomputer Systems
Logic Circuits and Microcomputer Systems
Algorithms for Interface Timing Verification
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
A new interface specification methodology and its application to transducer synthesis
A new interface specification methodology and its application to transducer synthesis
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We formulate several device timing characteristics, andintroduce the concept of separation bounds to modeldevices‘ waveform timing specifications. Separation bounds areused to verify that the produced timings of one device‘s signalssatisfy the required timings of another device to which it is tobe connected. We show that even if we know the bounds on twopairs of signal events, say (u, v) and (v, w), we cannotalways deduce the correct bounds on (u, w). However, we showthat the shortest path method proposed in [4]—to deducetight constraints from a partial specification—is safe, in thesense that an affirmative answer to satisfiability istrustworthy while a negative answer may be pessimistic.