Hardware/software partitioning and minimizing memory interface traffic
EURO-DAC '94 Proceedings of the conference on European design automation
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
A codesign case study in computer graphics
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
CASTLE: an interactive environment for HW-SW Co-Design
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
| Hi-index | 0.00 |
A commonly accepted technique in hardware/software co-design is to implement as many system functions as possible in software and to move performance critical functions into special-purpose external hardware in order to either satisfy timing constraints or reduce the overall execution time of a program - this is known as "software acceleration". This paper investigates the limits to the performance enhancements obtainable using software acceleration techniques. A practical target architecture, based on the use of programmable logic, is used to illustrate the problems associated with software acceleration. It is shown that normally little benefit can be obtained by applying software acceleration methods to general-purpose applications. Whereas software acceleration can profitably be used in a limited number of special-purpose applications, a designer would probably be better off developing ASIP components, based on heterogeneous multiprocessor architectures.