Synthesis and simulation of digital systems containing interacting hardware and software components
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Rewriting executable files to measure program behavior
Software—Practice & Experience
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Communication and interface synthesis on a rapid protoyping hardware/software codesign system
Proceedings of the 11th international symposium on System synthesis
Proceedings of the conference on Design, automation and test in Europe
Design of embedded systems: formal models, validation, and synthesis
Readings in hardware/software co-design
An Automatic Hardware-Software Partitioner Based on the Possibilistic Programming.
EDTC '96 Proceedings of the 1996 European conference on Design and Test
The Interplay of Run-Time Estimation and Granularity in HW/SW Partitioning
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Software acceleration using programmable logic: is it worth the effort?
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Automatic generation of interprocess communication in the PARAGON system
RSP '96 Proceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)
Partitioning of Hardware-Software Embedded Systems: A Metrics-based Approach
Integrated Computer-Aided Engineering
Using Genetic Algorithms for solving partitioning problem in codesign
IWANN '03 Proceedings of the 7th International Work-Conference on Artificial and Natural Neural Networks: Part II: Artificial Neural Nets Problem Solving Methods
An embedded CDMA-receiver A design example
Integration, the VLSI Journal
Pipelining-based tradeoffs for hardware/software codesign of multimedia systems
EURO-PDP'00 Proceedings of the 8th Euromicro conference on Parallel and distributed processing
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We introduce CASTLE, a design environment for embedded systems. Starting from an algorithmic specification in C++/VHDL, CASTLE helps a designer to quickly find a suitable, cost-effective implementation of his system. The designer manually partitions the algorithmic specification into hardware and software components and refines the hardware architecture step by step. CASTLE provides immediate feed-back by displaying the feasibility and consequences of each partitioning decision. After partitioning, CASTLE automatically outputs the hardware and software components as VHDL and C++ programs. These can then be simulated to validate the design partitioning. Highlights of the CASTLE design environment include support for product maintenance, arbitrary hardware architectures and full design control by the designer.