MIPS RISC architectures
Synthesis of instruction sets for pipelined microprocessors
DAC '94 Proceedings of the 31st annual Design Automation Conference
A tool for processor instruction set design
EURO-DAC '94 Proceedings of the conference on European design automation
Implementing fuzzy control systems using VHDL and statecharts
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
An extendable MIPS-I processor kernel in VHDL for hardware/software co-design
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Computer-Aided Hardware-Software Codesign
IEEE Micro
IEEE Micro Annual Index Volume 16, 1996
IEEE Micro
Instruction set selection for ASIP design
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
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In this paper, we show how hardware/software co-evaluation can be applied to instruction set definition. As a case study, we show the definition and evaluation of instruction set extensions for fuzzy processing. These instructions are based on the use of subword parallelism to fully exploit the processor's resources by processing multiple data streams in parallel. The proposed instructions are evaluated in software and hardware to gain a balanced view of the costs and benefits of each instruction. We have found that a simple instruction optimized to perform fuzzy rule evaluation offers the most benefit to improve fuzzy processing performance. The instruction set extensions are added to a RISC processor core based on the MIPS instruction set architecture. The core has been described in VHDL so that hardware implementations can be generated using logic synthesis.