Combinatorial algorithms for integrated circuit layout
Combinatorial algorithms for integrated circuit layout
PipeRench: a co/processor for streaming multimedia acceleration
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Iterative Computer Algorithms with Applications in Engineering: Solving Combinatorial Optimization Problems
Design and Test of Core-Based Systems on Chips
IEEE Design & Test
DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
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ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1
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Application-specific Systems-on-Chip (SoCs) introduce a set of various challenges for their interdisciplinary microelectronic implementation, from system theory (application) level over efficient CAD methods to suitable technologies, e. g. considering also reconfigurable hardware parts on different granularities. The paper sketches first major perspectives in architecture, design and application of Configurable Systems-on-Chip (CSoCs). The focus is the description of new CAD-algorithms for mapping automatized pre-synthesized IP-cores onto coarse-grain dynamically reconfigurable array architectures. Here, combinatorial optimization methods are combined with physical chip design algorithms, whereas dynamic reconfiguration of allocated hardware resources is considered.