Structured logic design with VHDL
Structured logic design with VHDL
Implementation of IEEE single-precision floating-point operations on FPGAs (abstract)
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Unstructured mesh computations on CCMs
Advances in Engineering Software - Special issue on large-scale analysis, design and intelligent synthesis environments
Computer Arithmetic Algorithms
Computer Arithmetic Algorithms
An Assessment of the Suitability of FPGA-Based Systems for Use in Digital Signal Processing
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
JHDL - An HDL for Reconfigurable Systems
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
A CAD Suite for High-Performance FPGA Design
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
On Sparse Matrix-Vector Multiplication with FPGA-Based System
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Communication issues in heterogeneous embedded systems
WPDRTS '96 Proceedings of the 4th International Workshop on Parallel and Distributed Real-Time Systems
Quantitative analysis of floating point arithmetic on FPGA based custom computing machines
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Hidden Markov modeling and fuzzy controllers in FPGAs
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Constrained motion control using vector potential fields
IEEE Transactions on Systems, Man, and Cybernetics, Part A: Systems and Humans
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In many scientific simulation codes, the bulk of the floating-point arithmetic required is done by a small number of compact computational kernels. In this paper, we explore the potential use of configurable computers to instantiate the hardware required for such kernels and, thus, improve their performance. We present algorithms and analysis for two such kernels: fast, problem-specific multipliers and the efficient evaluation of Taylor series. A novel aspect of the algorithm for Taylor series evaluation is that it takes advantage of the variable precision arithmetic available to a configurable computer. Experimental results obtained on a Xilinx field-programmable gate array (FPGA) are presented for the proposed algorithms.