Processor Enhancements for Media Streaming Applications
Journal of VLSI Signal Processing Systems
Reconfigurable signal processing and hardware architecture for broadband wireless communications
EURASIP Journal on Wireless Communications and Networking
Mobility '06 Proceedings of the 3rd international conference on Mobile technology, applications & systems
Addressing challenges of software radio
ICOSSE'06 Proceedings of the 5th WSEAS international conference on System science and simulation in engineering
Efficient resource sharing architecture for multistandard communication system
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
| Hi-index | 0.01 |
In this paper, we show the necessity of reconfigurable hardware for data and signal processing in wireless mobile terminals. We first identify the key processing power requirements for realizing a third generation wireless mobile terminal with multi-link and multi-standard capabilities. This is done on the basis of two world applications: a flexible mobile rake receiver for UMTS/W-CDMA and an OFDM decoder for high-speed wireless LAN protocols. We present a software-defined concept and a system implementation for the signal processing in these applications. The system is based on a DSP for control-flow oriented tasks, dedicated hardware for predefined data-flow oriented tasks and reconfigurable hardware for software-defined data-flow oriented tasks. A new coarse-grained approach is used to implement the reconfigurable hardware, which is in the form of an array of processing elements and also contains resource management mechanisms. The features and programming concepts of the reconfigurable hardware are emphasized further in the text.