A methodology and design environment for DSP ASIC fixed point refinement
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Multi-Carrier Digital Communications: Theory and Applications of Ofdm
Multi-Carrier Digital Communications: Theory and Applications of Ofdm
Wireless OFDM Systems: How to Make Them Work?
Wireless OFDM Systems: How to Make Them Work?
PICARD: Platform Concepts for Prototyping and Demonstration of High Speed Communication Systems
RSP '02 Proceedings of the 13th IEEE International Workshop on Rapid System Prototyping (RSP'02)
A simple transmit diversity technique for wireless communications
IEEE Journal on Selected Areas in Communications
From theory to practice: an overview of MIMO space-time coded wireless systems
IEEE Journal on Selected Areas in Communications
Rapid industrial prototyping and SoC design of 3G/4G wireless systems using an HLS methodology
EURASIP Journal on Embedded Systems
Simulation and emulation of MIMO wireless baseband transceivers
EURASIP Journal on Wireless Communications and Networking - Special issue on simulators and experimental testbeds design and development for wireless networks
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To assess the performance of forthcoming 4th generation wireless local area networks, the algorithmic functionality is usually modelled using a high-level mathematical software package, for instance, Matlab. In order to validate the modelling assumptions against the real physical world, the high-level functional model needs to be translated into a prototype. A systematic system design methodology proves very valuable, since it avoids, or, at least reduces, numerous design iterations. In this paper, we propose a novel Matlab-to-hardware design flow, which allows to map the algorithmic functionality onto the target prototyping platform in a systematic and reproducible way. The proposed design flow is partly manual and partly tool assisted. It is shown that the proposed design flow allows to use the same testbench throughout the whole design flow and avoids time-consuming and error-prone intermediate translation steps.