Timing analysis for synthesis in microprocessor interface design

Authors:
Marco A. Escalante;Nikitas J. Dimopoulos
Affiliations:
Department of Electrical and Computer Engineering, University of Victoria, BC Canada, PO Box 3055, Victoria BC, V8W 3P6 Canada;Department of Electrical and Computer Engineering, University of Victoria, BC Canada, PO Box 3055, Victoria BC, V8W 3P6 Canada
Venue:
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Year:
1994

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