The design of an asynchronous microprocessor
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Performance analysis and optimization of asynchronous circuits
Performance analysis and optimization of asynchronous circuits
An approach to symbolic timing verification
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Predicting deterministic execution times of real-time programs
Predicting deterministic execution times of real-time programs
Performance of iterative computation in self-timed rings
Journal of VLSI Signal Processing Systems - Special issue: asynchronous circuit design for VLSI signal processing
A general approach to performance analysis and optimization of asynchronous circuits
A general approach to performance analysis and optimization of asynchronous circuits
Min-max linear programming and the timing analysis of digital circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Symbolic timing verification of timing diagrams using Presburger formulas
DAC '97 Proceedings of the 34th annual Design Automation Conference
Bounded Delay Timing Analysis of a Class of CSP Programs
Formal Methods in System Design
Making complex timing relationships readable: Presburger formula simplicication using don't cares
DAC '98 Proceedings of the 35th annual Design Automation Conference
A Practical Decision Procedure for Arithmetic with Function Symbols
Journal of the ACM (JACM)
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems
IEEE Transactions on Computers
Algorithms for Interface Timing Verification
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Response Time Properties of Some Asynchronous Circuits
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Temporal Properties of Self-Timed Rings
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
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We extend the TSE [14] timing analysis algorithm into the symbolic domain, that is, we allow symbolic variables to be used to specify unknown parameters of the model (essentially, unknown delays) and verification algorithms which are capable of identifying not just failure or success, but also the constraints on these symbolic variables which will ensure successful verification. The two main contributions are 1) an iterative algorithm which continuously narrows down the domain of interest and 2) a practical method for reducing the representation of symbolic expressions containing minimizations and maximizations defined a given domain. We report experimental results for several asynchronous circuits to demonstrate that symbolic analysis is feasible and that the output provided is what a (or perhaps a synthesis tool) would often want to know.