A 800 MHz System-on-Chip for Wireless Infrastructure Applications

  • Authors:

  • Sanjive Agarwala;Paul Wiley;Arjun Rajagopal;Anthony Hill;Raguram Damodaran;Lewis Nardini;Tim Anderson;Steven Mullinnix;Jose Flores;Heping Yue;Abhijeet Chachad;John Apostol;Kyle Castille;Usha Narasimha;Tod Wolf;NS Nagaraj;Manjeri Krishnan;Luong Nguyen;Todd Kroeger;Mike Gill;Peter Groves;Bill Webster;Joel Graber;Christine Karlovich

  • Affiliations:

  • -;-;-;-;-;-;-;-;-;-;-;-;-;-;-;-;-;-;-;-;-;-;-;-

  • Venue:
  • VLSID '04 Proceedings of the 17th International Conference on VLSI Design
  • Year:
  • 2004

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Abstract

The 800MHz System-on-Chip implements the C64x VLIWDSP VelociTI.2TM Architecture and delivers 6400 MIPS,3200 16-bit MMACs, 6400 8-bit MMACs at 0.17mW/MMAC (8 bit). The chip is implemented in state of theart 90 nm CMOS technology with 7-layer coppermetalization. The core dissipates 1080 mW at 800 MHz,1.2V. The system-on-chip is targeted for high performancewireless infrastructure application. It has an 8-way VLIWDSP core, a 2-level memory system, and an I/O bandwidthof 3.2GB/s.