Synthesis of an efficient controlling structure for post-silicon clock skew minimization

Authors:
Yu-Chien Kao;Hsuan-Ming Chou;Kun-Ting Tsai;Shih-Chieh Chang
Affiliations:
National Tsing Hua University, HsinChu, Taiwan;National Tsing Hua University, HsinChu, Taiwan;National Tsing Hua University, HsinChu, Taiwan;National Tsing Hua University, HsinChu, Taiwan
Venue:
Proceedings of the International Conference on Computer-Aided Design
Year:
2010

Citing 3
Cited 1

Interconnect design for deep submicron ICs

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Value assignment of Adjustable Delay Buffers for clock skew minimization in multi-voltage mode designs

Proceedings of the 2009 International Conference on Computer-Aided Design

A robust architecture for post-silicon skew tuning

Proceedings of the International Conference on Computer-Aided Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

Clock skew minimization has been an important design constraint. However, due to the complexity of Process, Voltage, and Temperature (PVT) variations, the minimization of clock skew has faced a great challenge. To overcome the influence of PVT variations, several previous works proposed Post Silicon Tuning (PST) architecture to dynamically balance the skew of a clock tree. In the PST architecture, there are two main components: Adjustable Delay Buffer (ADB) and Phase Detector (PD). Most previous works focus on determining good positions of ADBs in a PST design. In this paper, we first show that which pairs of FFs are connected to PDs, called PD structure, also greatly influence the complexity of hardware control for a PST design. Without careful planning of a PD structure, we need large number of control signals to adjust the delays of ADBs. In addition, we also show that a PD structure may influence the accuracy of the clock skew. Among possible connection structures, this paper proposes an efficient PD structure which not only simplifies the hardware control but also minimizes the clock skew of a PST design.