Optimal wiresizing for interconnects with multiple sources
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simulation and sensitivity analysis of transmission line circuits by the characteristics method
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Global interconnect sizing and spacing with consideration of coupling capacitance
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Interconnect layout optimization under higher-order RLC model
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
MCM interconnect design using two-pole approximation
Proceedings of the conference on Design, automation and test in Europe
Simultaneous shield insertion and net ordering under explicit RLC noise constraint
Proceedings of the 38th annual Design Automation Conference
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Timing modeling and optimization under the transmission line model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power characteristics of inductive interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-aggressor capacitive and inductive coupling noise modeling and mitigation
Microelectronics Journal
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This paper presents a sensitivity-based wiresizing algorithm for interconnect delay optimization of lossy transmission line topology under MCM technologies. Our approach computes the maximum delay and its sensitivities with respect to the widths of wires in the topology via high order moments based on an exact moment matching model. Compared with other approaches, it achieves analytical sensitivity computation and calculates higher order moments (sensitivities) recursively from lower order moments for tree network. It can yield optimal wiresizing solution for interconnect delay minimization. Experiments show that the delay estimation using high order moments is very accurate compared with SPICE simulation and our approach can reduce the maximum rising delay by over 60% with small penalty in routing area. Besides delay optimization, the final solution eliminates the overshooting of response waveform and is robust under parameter variations.