Fast disjoint transistor networks from BDDs
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
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This paper presents a unified theory to build transistor networks through Binary Decision Diagrams - BDDs. It is able to obtain transistor networks with transistor count near to the best case of other methods presented in the literature. As a result, a pass transistor network implementation is automatically generated for XOR-like gates, since static CMOS performs badly. Similarly, a static CMOS topology is preferred for the generation of NAND-like gates, on which Pass Transistor Logic is not optimal. Variations on the derivation of transistor networks from BDDs are extensively discussed.