Transistor-Level Optimization of Supergates

  • Authors:
  • Dimitris Kagaris;Themistoklis Haniotakis

  • Affiliations:
  • Southern Illinois University, Carbondale, IL;Southern Illinois University, Carbondale, IL

  • Venue:
  • ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
  • Year:
  • 2006

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Abstract

The chip area and delay in digital VLSI design depends on the number of transistors that are used for the logic gates involved. While the determination of a series-parallel implementation can be straightforward once a simplified expression of the function is available, this may not be an optimum solution. In the current paper an improved approach for determining a satisfactory solution for complex gates is presented. Experimental results demonstrate the efficiency of the approach.