Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits

Authors:
Paulo F. Butzen;Leomar S. da Rosa, Jr;Erasmo J. D. Chiappetta Filho;André I. Reis;Renato P. Ribas
Affiliations:
Federal University of Rio Grande do Sul, Av. Bento Gonçalves, 9500, Bloco IV, CEP 91501-970, Porto Alegre, RS, Brazil;Federal University of Pelotas, Rua Gomes Carneiro, 1, CEP 96010-610, Pelotas, RS, Brazil;Federal University of Rio Grande do Sul, Av. Bento Gonçalves, 9500, Bloco IV, CEP 91501-970, Porto Alegre, RS, Brazil;Federal University of Rio Grande do Sul, Av. Bento Gonçalves, 9500, Bloco IV, CEP 91501-970, Porto Alegre, RS, Brazil;Federal University of Rio Grande do Sul, Av. Bento Gonçalves, 9500, Bloco IV, CEP 91501-970, Porto Alegre, RS, Brazil
Venue:
Microelectronics Journal
Year:
2010

Citing 6
Cited 0

Gate oxide leakage current analysis and reduction for VLSI circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On estimating impact of loading effect on leakage current in sub-65nm scaled CMOS circuits based on Newton-Raphson method

Proceedings of the 44th annual Design Automation Conference
A methodology for transistor-efficient supergate design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
UDSM subthreshold leakage model for NMOS transistor stacks

Microelectronics Journal
Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Leakage currents are gaining importance as design parameters in nanometer CMOS technologies. A novel leakage current estimation method, which takes into account the dependency of leakage mechanisms, is proposed for general CMOS complex gates, including non-series-parallel transistor arrangements, not covered by existing approaches. The main contribution of this work is a fast, accurate, and systematic procedure to determine the potentials at transistor network nodes for calculating standby static currents. The proposed method has been validated through electrical simulations, showing an error smaller than 7% and an 80x speed-up when comparing to electrical simulation.