On estimating impact of loading effect on leakage current in sub-65nm scaled CMOS circuits based on Newton-Raphson method

Authors:
Ashesh Rastogi;Wei Chen;Sandip Kundu
Affiliations:
University of Massachusetts, Amherst, MA;University of Massachusetts, Amherst, MA;University of Massachusetts, Amherst, MA
Venue:
Proceedings of the 44th annual Design Automation Conference
Year:
2007

Citing 7
Cited 2

COSMOS: a compiled simulator for MOS circuits

DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling

Proceedings of the 40th annual Design Automation Conference
Efficient techniques for gate leakage estimation

Proceedings of the 2003 international symposium on Low power electronics and design
Statistical analysis of subthreshold leakage current for VLSI circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Gate oxide leakage current analysis and reduction for VLSI circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect

VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems

Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits

Microelectronics Journal
Routing resistance influence in loading effect on leakage analysis

PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation

Quantified Score

Hi-index	0.00

Visualization

Abstract

Different sources of leakage can affect each other by interacting through resulting intermediate node voltages. This is known as the loading effect, In this paper, we propose a pattern dependent steady state leakage estimation technique that incorporates loading effect and addresses the three dominant sources of leakage, namely the sub-threshold, gate oxide and band-to-band tunneling leakages. We have developed a compact leakage model that supports iteration over node voltages based on Newton-Raphson method. The proposed estimation technique based on the compact model improves performance and capacity over SPICE. We report a speed up of 18,000X over SPICE. Results show that loading effect is a significant factor in leakage and worsens with technology scaling.