Routing resistance influence in loading effect on leakage analysis

Authors:
Paulo F. Butzen;André I. Reis;Renato P. Ribas
Affiliations:
PGMICRO – UFRGS;PGMICRO – UFRGS;PGMICRO – UFRGS
Venue:
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2009

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Abstract

Leakage currents represent emergent design parameters in nanometer CMOS technologies. Leakage mechanisms interact with each other at device level (through device geometry and doping profile), at gate level (through intra-cell node voltage) and at circuit level (through inter-cell node voltages). In this paper, the impact of loading effect in the standby power consumption is evaluated in relation to the gate oxide leakage magnitude and the routing resistivity. Simulation results, considering a 32nm technology node, have demonstrated an increase of up to 15% in the total circuit leakage dissipation due to the loading effect influenced by wire resistance.