Layout impact of resolution enhancement techniques: impediment or opportunity?
Proceedings of the 2003 international symposium on Physical design
Design for Manufacturability and Statistical Design: A Comprehensive Approach
Design for Manufacturability and Statistical Design: A Comprehensive Approach
Fast and Accurate OPC for Standard-Cell Layouts
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Nano-CMOS Design for Manufacturability: Robust Circuit and Physical Design for Sub-65nm Technology Nodes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Advanced Monte Carlo techniques in the simulation of CMOS devices and circuits
NMA'10 Proceedings of the 7th international conference on Numerical methods and applications
Designing via-configurable logic blocks for regular fabric
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Integrated circuits suffer from serious layout printability issues associated to the lithography manufacturing process. Regular layout designs are emerging as alternative solutions to help reducing these systematic subwavelength lithography variations. However, there is no metric to evaluate and compare the layout regularity of those regular designs and there is no methodology to link layout regularity to the reduction of process variations. In this paper we propose a new layout regularity metric called Fixed Origin Corner Square Inspection (FOCSI). We also provide a methodology using the Monte Carlo analysis to evaluate and understand the impact of regularity on process variability.