Design for Delay Testability in High-Speed Digital ICs
Journal of Electronic Testing: Theory and Applications
Bridging the Testing Speed Gap: Design for Delay Testability
ETW '00 Proceedings of the IEEE European Test Workshop
Multiple-Parameter CMOS IC Testing with Increased Sensitivity for IDDQ
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Comparison of Bridging Fault Simulation Methods
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A DFT Technique for High Performance Circuit Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
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In his keynote speech at the 1997 VLSI Test Symposium, held in April in Monterey, California, Gadi Singer presented his view of the future of test and design for testability. In addition, Singer, general manager of design technology at Intel Corporation, where he has worked for 15 years, posed several challenges to the design and test community. Here, he summarizes his major points.