Power considerations in the design of the Alpha 21264 microprocessor
DAC '98 Proceedings of the 35th annual Design Automation Conference
Gate leakage reduction for scaled devices using transistor stacking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sleep transistor sizing and adaptive control for supply noise minimization considering resonance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Although there has been extensive research on controlling leakage power, the fact that leaky transistors can act as a damping element for supply noise has been long ignored or unnoticed in the design community. This paper investigates the leakage induced damping effect that helps suppress the supply noise. By developing physics-based impedance models for active and leakage currents, we show that leakage, particularly gate tunneling leakage, provides more damping than strong-inversion current. Simulations were performed in a 32nm CMOS technology to validate our models under PVT variations and to explore the voltage dependent behavior of this phenomenon. Design example utilizing leakage induced damping such as decap assignment is discussed with results showing 15.6% saving in decap area.