Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage control with efficient use of transistor stacks in single threshold CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Runtime mechanisms for leakage current reduction in CMOS VLSI circuits1,2
Proceedings of the 2002 international symposium on Low power electronics and design
Evaluating Run-Time Techniques for Leakage Power Reduction
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Maximum Leakage Power Estimation for CMOS Circuits
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
Gate leakage reduction for scaled devices using transistor stacking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Technology mapping for low leakage power and high speed with hot-carrier effect consideration
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Circuit activity based logic synthesis for low power reliable operations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Models and algorithms for bounds on leakage in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis of power-managed sequential components based on computational kernel extraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power efficient technology decomposition and mapping under an extended power consumption model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Power consumption due to the temperature-dependent leakage current becomes a dominant part of the total power dissipation in systems using nanometer-scale process technology. To obtain the minimum power consumption for different operating conditions, logic synthesis tools are required to take into consideration the leakage power as well as the operating characteristics during the optimization. Conventional logic synthesis flows consider dynamic power only and use an over-simplified cost function in modeling the total power consumption of the logic network. In this paper, we propose a complete model of the total power consumption of the logic network, which includes both the active and standby sub-threshold leakage power, and the operating duty cycle of the applications. We also propose a least leakage vector (LLV) assisted technology mapping algorithm to optimize the total power of the final mapped network. Instead of finding the LLV after the logic network is synthesized and mapped, we use the LLV found in the technology-decomposed network to help in obtaining the lowest total power match during technology mapping. Experimental results on MCNC benchmarks show that on average more than 30% reduction in total power consumption is obtained comparing with the conventional low power technology mapping algorithm.