Leakage-suppressed clock-gating circuit with zigzag super cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-VDD LSIs

Authors:
Kyeong-Sik Min;Hun-Dae Choi;H.-Y. Choi;Hiroshi Kawaguchi;Takayasu Sakurai
Affiliations:
School of Electrical Engineering, Kookmin University, Seoul, Korea;School of Electrical Engineering, Kookmin University, Seoul, Korea;School of Electrical Engineering, Kookmin University, Seoul, Korea;Department of Computer Systems Engineering, Kobe University, Kobe, Japan and Institute of Industrial Science, Center for Collaborative Research, University of Tokyo, Tokyo, Japan;Institute of Industrial Science, Center for Collaborative Research, University of Tokyo, Tokyo, Japan
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2006

Citing 2
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Abstract

As a candidate for the clock-gating scheme, Zigzag Super Cut-off CMOS (ZSCCMOS) has proposed to reduce not only the switching power but also the leakage power. Due to its fast wakeup nature, the ZSCCMOS can be best suited to the clock-gating scheme. The wakeup time of the ZSCCMOS is estimated to be 12 times faster than the conventional Super Cut-off CMOS (SCCMOS) in 70-nm process technology. From the measurement of wakeup time in 0.6-µm technology, it is observed to he eight times faster than the conventional scheme. Layout area, power, and delay overhead of the ZSCCMOS are discussed and analyzed in this paper.