Simultaneous power and thermal integrity driven via stapling in 3D ICs
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Due to the high speed and low power trends, the power distribution network (PDN) in multi-layer printed circuit boards (PCBs) plays a pivotal role in terms of system performance. This paper presents an efficient analysis method for the irregular shaped power/ground plane pair considering the effect of densely populated power/ground and signal vias in thefrequency domain. The plane is divided based on geometric properties and modeled by the parallel-plate transmission line theory. For examination of various via effects, we have modeled vias according to their properties such as power, ground and signal. Using a conventional circuit simulator, the input-and trans-impedance of power/ground planes are investigated. Since the proposed method is accurate as well as fast, it can be efficiently applied to multi-layered PCB structures at the early design stage.