System-level synthesis of low-power hard real-time systems
DAC '97 Proceedings of the 34th annual Design Automation Conference
Using Performance Counters for Runtime Temperature Sensing in High-Performance Processors
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 11 - Volume 12
Balancing power consumption in multiprocessor systems
Proceedings of the 1st ACM SIGOPS/EuroSys European Conference on Computer Systems 2006
Temperature-aware leakage minimization technique for real-time systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Proceedings of the 45th annual Design Automation Conference
Hardware Trojan horse detection using gate-level characterization
Proceedings of the 46th Annual Design Automation Conference
Energy efficient multiprocessor task scheduling under input-dependent variation
Proceedings of the Conference on Design, Automation and Test in Europe
Energy minimization for real-time systems with non-convex and discrete operation modes
Proceedings of the Conference on Design, Automation and Test in Europe
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We have developed a system architecture, measuring and modeling techniques, and algorithms for on-line power and energy optimization and thermal management. The starting point for our approach is a simple and small gate-level network that can be used for real-time and low overhead measurement of temperature on chip positions where our network gates are placed. We use linear programming and interpolation to calculate the temperature at any arbitrary point of the integrated circuit. The periodic calculations of the temperature are used to estimate locally dissipated energies, which are consequently used to derive the most efficient use of operational times to minimize the overall leakage energy. All concepts and algorithms are experimentally validated using a simulation platform that consists of the Alpha 21364 processor and the SPEC benchmarks.