Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
The design of RPM: an FPGA-based multiprocessor emulator
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Multiprocessor mapping of process networks: a JPEG decoding case study
Proceedings of the 15th international symposium on System Synthesis
The future of multiprocessor systems-on-chips
Proceedings of the 41st annual Design Automation Conference
BEE2: A High-End Reconfigurable Computing System
IEEE Design & Test
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC
Journal of VLSI Signal Processing Systems
Proceedings of the 43rd annual Design Automation Conference
A practical FPGA-based framework for novel CMP research
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Distributed Simulation: A Case Study in Design and Verification of Distributed Programs
IEEE Transactions on Software Engineering
Software Performance Estimation in MPSoC Design
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Analyzing composability of applications on MPSoC platforms
Journal of Systems Architecture: the EUROMICRO Journal
Multithreaded simulation for synchronous dataflow graphs
Proceedings of the 45th annual Design Automation Conference
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Multi-processors are increasingly being used in modern embedded systems for reasons of power and speed. These systems have to support a large number of applications and standards, in different combinations, called use-cases. The key challenges are designing efficient systems handling all these usecases; this requires fast exploration of software and hardware alternatives with accurate performance evaluation. In this paper, we present a system-level FPGA-based simulation methodology for performance evaluation of applications on multiprocessor platforms. We observe that for multiple applications sharing an MPSoC platform, dynamic arbitration can cause deadlock in simulation. We use conservative Parallel Discrete Event Simulation (PDES) for simulation of these use-cases. We further note that conservative PDES is inefficient so we present a new PDES methodology that avoids causality errors by detecting them in advance.We call our new approach as smart conservative PDES. It is scalable in the number of use-cases and number of simulated processors and is 15% faster than conservative PDES. We further present results of a case-study of two real life applications. We used our simulation technique to do a design space exploration for optimal buffer space for JPEG and H263 decoders.