Software Performance Estimation in MPSoC Design

  • Authors:
  • M. Oyamada;F. R. Wagner;M. Bonaciu;W. Cesario;A. Jerraya

  • Affiliations:
  • UFRGS, Inst. de Informatica, Porto Alegre;UFRGS, Inst. de Informatica, Porto Alegre;-;-;-

  • Venue:
  • ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
  • Year:
  • 2007

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Abstract

Estimation tools are a key component of system-level methodologies, enabling a fast design space exploration. Estimation of software performance is essential in current software-dominated embedded systems. This work proposes an integrated methodology for system design and performance analysis. An analytic approach based on neural networks is used for high-level software performance estimation. At the functional level, this analytic tool enables a fast evaluation of the performance to be obtained with selected processors, which is an essential task for the definition of a "golden" architecture. From this architectural definition, a tool that refines hardware and software interfaces produces a bus-functional model. A virtual prototype is then generated from the bus-functional model, providing a global, cycle-accurate simulation model and offering several features for design validation and detailed performance analysis. Our work thus combines an analytic approach at functional level and a simulation-based approach at bus functional level. This provides an adequate trade-off between estimation time and precision. A multiprocessor platform implementing an MPEG4 encoder is used as case study, and the analytic estimation results in errors only up to 17% when compared to the virtual platform simulation. On the other hand, the analytic estimation takes only 17 seconds, against 10 minutes using the cycle-accurate simulation model.