A compilation-based software estimation scheme for hardware/software co-simulation
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Timed compiled-code simulation of embedded software for performance analysis of SOC design
Proceedings of the 39th annual Design Automation Conference
System level design with spade: an M-JPEG case study
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation
Proceedings of the 40th annual Design Automation Conference
A Generic RTOS Model for Real-time Systems Simulation with SystemC
Proceedings of the conference on Design, automation and test in Europe - Volume 3
An integrated hardware/software approach for run-time scratchpad management
Proceedings of the 41st annual Design Automation Conference
Design and programming of embedded multiprocessors: an interface-centric approach
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC
Journal of VLSI Signal Processing Systems
A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels
IEEE Transactions on Computers
An efficient and portable scheduler for RTOS simulation and its certified integration to SystemC
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Exploiting coarse-grained task, data, and pipeline parallelism in stream programs
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
TotalProf: a fast and accurate retargetable source code profiler
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Native MPSoC co-simulation environment for software performance estimation
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Fast and accurate source-level simulation of software timing considering complex code optimizations
Proceedings of the 48th Design Automation Conference
Dominator homomorphism based code matching for source-level simulation of embedded software
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Hybrid source-level simulation of data caches using abstract cache models
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Performance simulation of software for Multiprocessor System-on-a-Chips (MPSoC) suffers from poor tool support. Cycle accurate simulation at Instruction Set Simulation level is too slow and inefficient for any design of realistic size. Behavioral simulation, though useful for functional analysis at high level, does not provide any performance information that is crucial for design and analysis of MPSoC implementations. As a consequence, designers are often reduced to manually annotate performance information onto behavioral models, which contributes further to inefficiency and inaccuracy. In this paper, we use structural performance models to provide fast and accurate simulation of software for MPSoC. We generate structural models automatically using GCC with accurate performance annotation while considering optimizations for instruction selection, branch prediction, and pipeline interlock. Our structural models are able to simulate at several orders of magnitude faster than ISS and provide less than 1% error on performance estimation. These models allow realistic MPSoC design space explorations based on performance characteristics with simulation speed comparable to behavioral simulation. We validate our simulation models with several benchmarks and demonstrate our approach with a design case study of an MPEG-2 decoder.