DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
SPLASH: Stanford parallel applications for shared-memory*
SPLASH: Stanford parallel applications for shared-memory*
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
A Complete Network-On-Chip Emulation Framework
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Implementation analysis of NoC: a MPSoC trace-driven approach
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Fast, Accurate and Detailed NoC Simulations
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
The FAST methodology for high-speed SoC/computer simulation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
A Fast Emulation-Based NoC Prototyping Framework
RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
FastFwd: an efficient hardware acceleration technique for trace-driven network-on-chip simulation
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
EURO-PDP'00 Proceedings of the 8th Euromicro conference on Parallel and distributed processing
An Efficient Power-Aware Optimization for Task Scheduling on NoC-based Many-core System
CIT '10 Proceedings of the 2010 10th IEEE International Conference on Computer and Information Technology
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The need for hardware acceleration of Network-on-Chip (NoC) simulation has been motivated by their growing complexity and large design space. NoC simulation can exploit the inherent concurrency in hardware by using FPGA based emulators. For trace-driven NoC emulators, we enhance this raw hardware speedup by exploiting the traffic characteristics for a more efficient utilization of hardware. We propose a technique, OTO-NoC-Sim, to reduce NoC emulation time by scheduling network transactions in an out-of-time order. Our simulation technique addresses the challenges arising out of an out-of-time-order scheduling in maintaining the correctness of statistics measured. Our experiments indicate that our proposed technique reduces the average emulation time by 3x for multi-threaded applications and by 3.5x for multi-programmed benchmarks when compared to a conventional FPGA emulation.