Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
AI Game Programming Wisdom
Genetic Algorithms in Engineering Systems
Genetic Algorithms in Engineering Systems
OpenMP: An Industry-Standard API for Shared-Memory Programming
IEEE Computational Science & Engineering
Energy-Aware Runtime Scheduling for Embedded-Multiprocessor SOCs
IEEE Design & Test
Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Task Concurrency Management Experiment for Power-Efficient Speed-Up of Embedded MPEG4 IM1 Player
ICPP '00 Proceedings of the 2000 International Workshop on Parallel Processing
Fuzzy Logic for Embedded Systems Applications
Fuzzy Logic for Embedded Systems Applications
Modern Data Warehousing, Mining, and Visualization: Core Concepts
Modern Data Warehousing, Mining, and Visualization: Core Concepts
Low-Latency Virtual-Channel Routers for On-Chip Networks
Proceedings of the 31st annual international symposium on Computer architecture
Microarchitectural techniques for power gating of execution units
Proceedings of the 2004 international symposium on Low power electronics and design
A low latency router supporting adaptivity for on-chip interconnects
Proceedings of the 42nd annual Design Automation Conference
A Reconfiguration Manager for Dynamically Reconfigurable Hardware
IEEE Design & Test
REPLICA2Pro: task relocation by bitstream manipulation in virtex-II/Pro FPGAs
Proceedings of the 3rd conference on Computing frontiers
An EDF schedulability test for periodic tasks on reconfigurable hardware devices
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Exploring Fault-Tolerant Network-on-Chip Architectures
DSN '06 Proceedings of the International Conference on Dependable Systems and Networks
Physical design methodology of power gating circuits for standard-cell-based design
Proceedings of the 43rd annual Design Automation Conference
Design space exploration for multicore architectures: a power/performance/thermal view
Proceedings of the 20th annual international conference on Supercomputing
Software/Hardware Co-Scheduling for Reconfigurable Computing Systems
FCCM '07 Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Efficient operating system scheduling for performance-asymmetric multi-core architectures
Proceedings of the 2007 ACM/IEEE conference on Supercomputing
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Analysis and approximation of optimal co-scheduling on chip multiprocessors
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs
IEEE Computer Architecture Letters
System-level exploration of run-time clusterization for energy-efficient on-chip communication
Proceedings of the 2nd International Workshop on Network on Chip Architectures
A Fuzzy Logic Reconfiguration Engine for Symmetric Chip Multiprocessors
CISIS '10 Proceedings of the 2010 International Conference on Complex, Intelligent and Software Intensive Systems
Data cache-energy and throughput models: design exploration for embedded processors
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
Analytical Evaluation of Energy and Throughput for Multilevel Caches
UKSIM '10 Proceedings of the 2010 12th International Conference on Computer Modelling and Simulation
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting unbalanced thread scheduling for energy and performance on a CMP of SMT processors
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
Model Approximation for Discrete-Time State-Delay Systems in the T–S Fuzzy Framework
IEEE Transactions on Fuzzy Systems
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Multicore architectures offer an amount of parallelism that is often underutilized, as a result these underutilized resources become a liability instead of advantage. Inefficient resource sharing on the chip can have a negative impact on the performance of an application and may result in greater energy consumption. A large body of research now focuses on reconfigurable multicore architectures in order to support algorithms to find optimal solutions for improved energy and throughput balance. An ideal system would be able to optimize such reconfigurable systems to a level that optimum resources are allocated to a particular workload and all the other underutilized resources remain inactive for greater energy savings. This paper presents a fuzzy logic based reconfiguration engine targeted to optimize a multicore architecture according to the workload requirements for optimum balance between power and performance of the system. The proposed fuzzy logic reconfiguration engine is designed around a 16-core SCMP architecture comprising of reconfigurable cache memories, power gated cores and adaptive on-chip network routers for minimizing leakage energy effects for inactive components. A coarse grained architecture was selected for being able to reconfigure faster, thus making it feasible to be used for runtime adaptation schemes. The presented architecture is analyzed over a set of OpenMP based parallel benchmarks and results show significant energy savings in all cases.