IEEE Transactions on Computers
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Performance characteristics of architectural features of the IBM RISC System/6000
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Generation and analysis of very long address traces
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
A graphical comparison of RISC processors
ACM SIGARCH Computer Architecture News
Performance evaluation of instruction scheduling on the IBM RISC System/6000
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
The impact of unresolved branches on branch prediction scheme performance
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Characterization of alpha AXP performance using TP and SPEC workloads
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Commercial workload performance in the IBM POWER2 RISC System/6000 processor
IBM Journal of Research and Development
Contrasting characteristics and cache performance of technical and multi-user commercial workloads
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Constructing instruction traces from cache-filtered address traces (CITCAT)
ACM SIGARCH Computer Architecture News
Trace-driven memory simulation: a survey
ACM Computing Surveys (CSUR)
Techniques for extracting instruction level parallelism on MIMD architectures
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
EXPLORER: a retargetable and visualization-based trace-driven simulator for superscalar processors
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
PopSPY: A PowerPC Instrumentation Tool for Multiprocessor Simulation
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
Trace-Driven Memory Simulation: A Survey
Performance Evaluation: Origins and Directions
Program balance and its impact on high performance RISC architectures
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Estimating critical region parallelism to guide platform retargeting
Proceedings of the 43rd annual Southeast regional conference - Volume 1
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