Retargetable cache simulation using high level processor models

Authors:
Rajiv Ravindran;Rajat Moona
Affiliations:
Indian Institute of Technology, Kanpur, U.P., 208016, India;Indian Institute of Technology, Kanpur, U.P., 208016, India
Venue:
ACSAC '01 Proceedings of the 6th Australasian conference on Computer systems architecture
Year:
2001

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Abstract

During processor design, it is often necessary to evaluate multiple cache configurations. This paper describes the design and implementation of a retargetable on-line cache simulator. The cache simulator has been implemented using a retargetable instruction set simulator from the Sim-nML [9] processor description language. The retargetability helps in cache simulation and evaluation much before the actual processor design.