Retargetable cache simulation using high level processor models
ACSAC '01 Proceedings of the 6th Australasian conference on Computer systems architecture
Retargetable Program Profiling Using High Level Processor Models
HiPC '01 Proceedings of the 8th International Conference on High Performance Computing
High Level Synthesis from Sim-nML Processor Models
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Virtual Prototypes in Developing Mobile Software Applications and Devices
PROFES '08 Proceedings of the 9th international conference on Product-Focused Software Process Improvement
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The current embedded systems design typically also involves the design of application specific integrated processors. In such scenarios, the designer needs to study various designs for choosing the best suited one with respect to the performance and the cost. The use of high level processor models along with automated tools is becoming popular in the performance study of the designs.This work involves the design and implementation of a Retargetable Functional Simulator Generator which is capable of generating a functional simulator for a processor given its high level model in the Sim-nML [6] language and a binary for the processor in ELF [1] format. The functional simulator so generated simulates the binary program for the described processor on any other host. It can also produce an uncompressed instruction trace for the binary program.