An accurate architectural simulator for ARM1136

Authors:
Hyo-Joong Suh;Sung Woo Chung
Affiliations:
School of Computer Science and Information Engineering, The Catholic University of Korea, Bucheon, Gyeonggido, Korea;Department of Computer Science, University of Virginia, Charlottesville, VA
Venue:
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
Year:
2005

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Abstract

Cycle-accurate simulators are basic tools to evaluate performance improvements of computer architecture. Before confirming of the architecture improvements using cycle-accurate simulation, the simulator itself should be validated. However, off-the-shelf processors have been continuously improved, though the cycle-accurate simulators were not reflected the improved features. Simulation results show that the difference between the IPC (Instruction Per Cycle) of the modified model for ARM1136 (Sim-ARM1136) and the IPC of the original model for ARM7 (Sim-Outorder) is 19%, on average, which is large enough to mislead the impact of architecture improvements.