Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Intra-Task Voltage Scheduling for Low-Energy, Hard Real-Time Applications
IEEE Design & Test
The Alpha 21264 Microprocessor
IEEE Micro
A scheduling model for reduced CPU energy
FOCS '95 Proceedings of the 36th Annual Symposium on Foundations of Computer Science
Temperature-aware microarchitecture: Modeling and implementation
ACM Transactions on Architecture and Code Optimization (TACO)
Static allocation of resources to communicating subtasks in a heterogeneous ad hoc grid environment
Journal of Parallel and Distributed Computing - Special issue: Algorithms for wireless and ad-hoc networks
Proceedings of the 2006 international symposium on Low power electronics and design
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
Die Stacking (3D) Microarchitecture
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Journal of VLSI Signal Processing Systems
Cross-Layer Collaborative In-Network Processing in Multihop Wireless Sensor Networks
IEEE Transactions on Mobile Computing
HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
Thermal-aware Steiner routing for 3D stacked ICs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Thermal balancing policy for streaming computing on multiprocessor architectures
Proceedings of the conference on Design, automation and test in Europe
Cost minimization while satisfying hard/soft timing constraints for heterogeneous embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proactive temperature balancing for low cost thermal management in MPSoCs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
ThermalScope: multi-scale thermal analysis for nanometer-scale integrated circuits
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
PPT: joint performance/power/thermal management of DRAM memory for multi-core systems
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Predict and act: dynamic thermal management for multi-core processors
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Dynamic thermal management using thin-film thermoelectric cooling
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Rotation Scheduling and Voltage Assignment to Minimize Energy for SoC
CSE '09 Proceedings of the 2009 International Conference on Computational Science and Engineering - Volume 02
Thermal-Aware Task Scheduling for 3D Multicore Processors
IEEE Transactions on Parallel and Distributed Systems
Dynamic and leakage energy minimization with soft real-time loop scheduling and voltage assignment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic thermal management in 3D multicore architectures
Proceedings of the Conference on Design, Automation and Test in Europe
Rotation scheduling: a loop pipelining algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Throughput maximization for periodic real-time systems under the maximal temperature constraint
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
Hi-index | 0.00 |
Chip multiprocessor (CMP) techniques have been implemented in embedded systems due to tremendous computation requirements. Three-dimension (3D) CMP architecture has been studied recently for integrating more functionalities and providing higher performance. The high temperature on chip is a critical issue for the 3D architecture. In this article, we propose an online thermal prediction model for 3D chips. Using this model, we propose novel task scheduling algorithms based on rotation scheduling to reduce the peak temperature on chip. We consider data dependencies, especially inter-iteration dependencies that are not well considered in most of the current thermal-aware task scheduling algorithms. Our simulation results show that our algorithms can efficiently reduce the peak temperature up to 8.1ˆC.