Value locality and load value prediction
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
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Computer architecture (2nd ed.): a quantitative approach
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Proceedings of the 27th annual international symposium on Computer architecture
Latency and energy aware value prediction for high-frequency processors
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PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
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ICS '03 Proceedings of the 17th annual international conference on Supercomputing
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HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
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ACM Transactions on Architecture and Code Optimization (TACO)
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Computer Languages, Systems and Structures
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This paper presents a design space exploration of a selective load value prediction scheme suitable for energy-aware Simultaneous Multi-Threaded (SMT) architectures. A load value predictor is an architectural enhancement which speculates over the results of a micro-processor load instruction to speed-up the execution of the following instructions. The proposed architectural enhancement differs from a classic predictor due to an improved selection scheme that allows to activate the predictor only when a miss occurs in the first level of cache. We analyze the effectiveness of the selective predictor in terms of overall energy reduction and performance improvement. To this end, we show how the proposed predictor can produce benefits (in terms of overall cost) when the cache size of the SMT architecture is reduced and we compare it with a classic non-selective load value prediction scheme. The experimental results have been gathered with a state-of-the-art SMT simulator running the SPEC2000 benchmark suite, both in SMT and non-SMT mode.