Memory data organization for improved cache performance in embedded processor applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Code placement techniques for cache miss rate reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
The wearable motherboard: a framework for personalized mobile information processing (PMIP)
Proceedings of the 39th annual Design Automation Conference
Principles of Program Analysis
Principles of Program Analysis
Accurate estimation of cache-related preemption delay
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
MIThril 2003: Applications and Architecture
ISWC '03 Proceedings of the 7th IEEE International Symposium on Wearable Computers
Cache optimization for embedded processor cores: An analytical approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Adaptive and fault tolerant medical vest for life-critical medical monitoring
Proceedings of the 2005 ACM symposium on Applied computing
Routing-aware scan chain ordering
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Wireless Sensor Networks for Health Monitoring
MOBIQUITOUS '05 Proceedings of the The Second Annual International Conference on Mobile and Ubiquitous Systems: Networking and Services
E-Textile Based Automatic Activity Diary for Medical Annotation and Analysis
BSN '06 Proceedings of the International Workshop on Wearable and Implantable Body Sensor Networks
On Optimization of E-Textile Systems Using Redundancy and Energy-Aware Routing
IEEE Transactions on Computers
Proceedings of the 43rd annual Design Automation Conference
A Wireless Body Area Sensor Network for Posture Detection
ISCC '06 Proceedings of the 11th IEEE Symposium on Computers and Communications
Algorithms
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
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Body-area sensor network or BAN-based health monitoring is increasingly becoming a popular alternative to traditional wired biomonitoring techniques. However, most biomonitoring applications need continuous processing of large volumes of data, as a result of which both power consumption and computation bandwidth turn out to be serious constraints for sensor network platforms. This has resulted in a lot of recent interest in design methods, modeling and software analysis techniques specifically targeted towards BANs and applications running on them. In this paper we show that appropriate optimization of the application running on the communication gateway of a wireless BAN and accurate modeling of the microarchitectural details of the gateway processor can lead to significantly better resource usage and power savings. In particular, we propose a method for deriving the optimal order in which the different sensors feeding the gateway processor should be sampled, to maximize cache re-use. Our case study using a faint fall detection application - from the geriatric care domain - which is fed by a number of smart sensors to detect physiological and physical gait signals of a patient show very attractive energy savings in the underlying processor. Alternatively, our method can be used to improve the sampling frequency of the sensors, leading to higher reliability and better response time of the application.