Leo: a system for cost effective 3D shaded graphics
SIGGRAPH '93 Proceedings of the 20th annual conference on Computer graphics and interactive techniques
SIGGRAPH '93 Proceedings of the 20th annual conference on Computer graphics and interactive techniques
Hierarchical Z-buffer visibility
SIGGRAPH '93 Proceedings of the 20th annual conference on Computer graphics and interactive techniques
Talisman: commodity realtime 3D graphics for the PC
SIGGRAPH '96 Proceedings of the 23rd annual conference on Computer graphics and interactive techniques
Triangle scan conversion using 2D homogeneous coordinates
HWWS '97 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Visibility culling using hierarchical occlusion maps
Proceedings of the 24th annual conference on Computer graphics and interactive techniques
Extending graphics hardware for occlusion queries in OpenGL
HWWS '98 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Neon: a single-chip 3D workstation graphics accelerator
HWWS '98 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Prefetching in a texture cache architecture
HWWS '98 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
A bandwidth-efficient architecture for media processing
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Optimal depth buffer for low-cost graphics hardware
HWWS '99 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Adaptive hierarchical visibility in a tiled architecture
HWWS '99 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Region-based caching: an energy-delay efficient memory architecture for embedded processors
CASES '00 Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems
The F-buffer: a rasterization-order FIFO buffer for multi-pass rendering
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
R-buffer: a pointerless A-buffer hardware architecture
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Real-Time Rendering
OpenGL Reference Manual: The Official Reference Document to OpenGL, Version 1.2
OpenGL Reference Manual: The Official Reference Document to OpenGL, Version 1.2
Efficient Conservative Visibility Culling Using the Prioritized-Layered Projection Algorithm
IEEE Transactions on Visualization and Computer Graphics
Delay streams for graphics hardware
ACM SIGGRAPH 2003 Papers
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The development of consumer-oriented 3D graphics pipeline increases the performance of 3D graphics hardware. In this paper, we propose a new method of hierarchical depth occlusion TOIGP. Generally, the 3D graphics pipeline itself consists of two distinct stages: geometry process and rasterization process. TOIGP is abbreviation of Triangle Occlusion In Geometry Process. In that way, many triangles can be occluded much earlier than traditional pipeline in real-time. TOIGP has less computation of hierarchical depth test than ATI's HyperZ. And the simulation proves that even 80.5 percents of triangle shaded can be occluded in the 3D future mark scene. This method can be implemented by adding a simple hardware in 3D graphic chip pipeline. As a result, the performance can be improved highly with simple extra hardware.