Runtime biased pointer reuse analysis and its application to energy efficiency

  • Authors:

  • Yao Guo;Saurabh Chheda;Csaba Andras Moritz

  • Affiliations:

  • Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA;Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA;Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA

  • Venue:
  • PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
  • Year:
  • 2003

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Abstract

Compiler-enabled memory systems have been successful in reducing chip energy consumption. A major challenge lies in their applicability in the context of complex pointer-intensive programs. State-of-the-art high precision pointer analysis techniques have limitations when applied to such programs, and therefore have restricted use. This paper describes runtime biased pointer reuse analysis to capture the behavior of pointers in programs of arbitrary complexity. The proposed technique is runtime biased and speculative in the sense that the possible targets for each pointer access are statically predicted based on the likelihood of their occurrence at runtime, rather than conservative static analysis alone. This idea implemented as a flow-sensitive dataflow analysis enables high precision in capturing pointer behavior, reduces complexity, and extends the approach to arbitrary programs. Besides memory accesses with good reuse/locality, the technique identifies irregular accesses that typically result in energy and performance penalties when managed statically. The approach is validated in the context of a compiler managed memory system targeting energy efficiency. On a suite of pointer-intensive benchmarks, the techniques increase the fraction of memory accesses that can be mapped statically to energy efficient memory access paths by 7-72%, giving a 4-31% additional L1 data cache energy reduction.